View IS61NVP102436A_4509290.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
1Mb x 36 and 2Mb x 18 36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
SEPTEMBER 2007 FEATURES
* 100 percent bus utilization * No wait cycles between Read and Write * Internal self-timed write cycle * Individual Byte Write Control * Single R/W (Read/Write) control pin * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Power Down mode * Common data inputs and data outputs * CKE pin to enable clock and suspend operation * JEDEC 100-pin TQFP and 165-ball PBGA packages * Power supply: NVP: VDD 2.5V ( 5%), VDDQ 2.5V ( 5%) NLP: VDD 3.3V ( 5%), VDDQ 3.3V/2.5V ( 5%) * Industrial temperature available * Lead-free available
DESCRIPTION
The 36 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -200 3.1 5 200 -166 3.5 6 166 Units ns ns MHz
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. A 09/13/07
1
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
BLOCK DIAGRAM
x 36: A [0:19] or x 18: A [0:20]
ADDRESS REGISTER
A2-A19 or A2-A20
1Mx36; 2Mx18 MEMORY ARRAY
MODE A0-A1
BURST ADDRESS COUNTER
A'0-A'1
K
DATA-IN REGISTER
CLK CKE CE CE2 CE2 ADV WE BWY X OE ZZ
CONTROL LOGIC K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
K
DATA-IN REGISTER
}
CONTROL REGISTER
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
(X=a,b,c,d or a,b)
36 or 18 DQx/DQPx
2
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
PIN CONFIGURATION -- 1M X 36, 165-Ball PBGA (TOP VIEW)
1 A B C D E F G H J K L M N P R NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC A 3 CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC NC 6 CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0* 7 CKE WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC NC 8 ADV OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. (Under Evaluation)
PIN DESCRIPTIONS
Symbol A A0, A1 ADV WE CLK CKE BWx (x=a-d) OE ZZ Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Byte Write Inputs Output Enable Power Sleep Mode MODE VDD NC DQx DQPx VDDQ VSS Burst Sequence Selection 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground
CE, CE2, CE2 Synchronous Chip Enable
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
3
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
165-PIN PBGA PACKAGE CONFIGURATION
1 2 3 4 5
2M x 18 (TOP VIEW)
6 7 8 9 10 11
A B C D E
F
NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE
A A NC DQb DQb DQb DQb
CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
BWb NC Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A
NC BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC
CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC A1* A0*
CKE WE Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC
ADV OE Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A
A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A
G H
J
NC
NC NC NC NC NC NC A
K
L
M N P R
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. (Under Evaluation)
PIN DESCRIPTIONS
Symbol A A0, A1 ADV WE CLK CKE BWx (x=a,b) OE ZZ Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Byte Write Inputs Output Enable Power Sleep Mode MODE VDD NC DQx DQPx VDDQ VSS Burst Sequence Selection 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground
CE, CE2, CE2 Synchronous Chip Enable
4
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
PIN CONFIGURATION
100-Pin TQFP
BWd
BWc BWb
BWa
CKE
ADV A
CLK WE
CE2
CE2 VDD Vss
OE
CE
NC BWb
BWa
CKE
ADV A
CE2
CE2 VDD Vss
CLK WE
A
A
A
A A
OE
NC
CE
A
A
A
DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc VDD VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VDD NC A A A A A A MODE A A A A A1 A0 NC NC Vss A A
DQPb DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa
NC NC NC VDDQ Vss NC NC DQb DQb Vss VDDQ DQb DQb VDD VDD NC Vss DQb DQb VDDQ Vss DQb DQb DQPb NC Vss VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE Vss NC NC NC A A A1 A0 A A A A A A A A VDD A A
A A
A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC
1M x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected
2M x 18
CE, CE2, CE2 Synchronous Chip Enable OE DQa-DQd DQPa-DQPd MODE VDD VSS VDDQ ZZ Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable
A CLK ADV BWa-BWd WE CKE Vss NC
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
5
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
STATE DIAGRAM
READ BEGIN READ WRITE DS READ DS WRITE BEGIN WRITE
READ
WRITE
READ
BURST DS
DESELECT BURST
BURST
WRITE
DS BURST READ WRITE
DS BURST WRITE
BURST
BURST
READ
SYNCHRONOUS TRUTH TABLE(1)
Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Notes:
1. 2. 3. 4.
Address Used N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address
CE H X X X L X L X L X L X X
CE2 X L X X H X H X H X H X X
CE2 CE X X H X L X L X L X L X X
ADV L L L H L H L H L H L H X
WE X X X X H X H X L X L X X
BWx BW X X X X X X X X L L H H X
OE X X X X L L H H X X X X X
CKE L L L L L L L L L L L L H
CLK

"X" means don't care. The rising edge of clock is symbolized by A continue deselect cycle can only be entered if a deselect cycle is executed first. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE).
6
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
ASYNCHRONOUS TRUTH TABLE(1)
Operation Sleep Mode Read Write Deselected Notes: ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L BWa BW X L H L H BWb BW X H L L H
1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE (x36)
Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L L L BWa BW X L H H H L H BWb BW X H L H H L H BWc BW X H H L H L H BWd BW X H H H L L H
1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 7
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TSTG PD IOUT VIN, VOUT VIN Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to VSS for I/O Pins Voltage Relative to VSS for for Address and Control Inputs Value -65 to +150 1.6 100 -0.5 to VDDQ + 0.3 -0.3 to 4.6 Unit C W mA V V
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61NLPx)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V 5% 3.3V 5% VDDQ 3.3V / 2.5V 5% 3.3V / 2.5V 5%
OPERATING RANGE (IS61NVPx)
Range Commercial Industrial 8 Ambient Temperature 0C to +70C -40C to +85C VDD 2.5V 5% 2.5V 5% VDDQ 2.5V 5% 2.5V 5%
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VSS VIN VDD(1) VSS VOUT VDDQ, OE = VIH Test Conditions IOH = -4.0 mA (3.3V) IOH = -1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) Min. 2.4 -- 2.0 -0.3 -5 -5 Max. -- 0.4 VDD + 0.3 0.8 5 5 Min. 2.0 -- 1.7 -0.3 -5 -5 2.5V Max. -- 0.4 VDD + 0.3 0.7 5 5 Unit V V V V A A
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-200 MAX x18 x36 450 475 390 260 270 260 270 450 475 -166 MAX x18 x36 400 400 450 450 340 250 260 250 260
Symbol Parameter ICC AC Operating Supply Current
Test Conditions Device Selected, OE = VIH, ZZ VIL, All Inputs 0.2V or VDD - 0.2V, Cycle Time tKC min. Device Deselected, VDD = Max., All Inputs VIL or VIH, ZZ VIL, f = Max. Device Deselected, VDD = Max., VIN VSS + 0.2V or VDD - 0.2V f=0
Temp. range Com. Ind. typ.(2) Com. Ind.
Unit mA
ISB
Standby Current TTL Input
mA
ISBI
Standby Current CMOS Input
Com. Ind. typ.(2)
105 110 30
105 110
105 110
105 110 30
mA
Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits 100A maximum leakage current when tied to VSS + 0.2V or VDD - 0.2V. 2. Typical values are measured at Vcc = 3.3V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
9
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317
Zo= 50
OUTPUT
+3.3V
OUTPUT
50
351
1.5V
5 pF Including jig and scope
Figure 1
Figure 2
10
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
2.5V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667
ZO = 50 OUTPUT
+2.5V
OUTPUT
50
1,538
1.25V
5 pF Including jig and scope
Figure 3
Figure 4
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
11
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol fmax tKC tKH tKL tKQ tKQX
(2) (2,3)
Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down
-200 Min. Max. -- 5 2 2 -- 1.5 1 -- -- 0 -- 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 -- -- 200 -- -- -- 3.1 -- -- 3.0 3.1 -- 3.0 -- -- -- -- -- -- -- -- -- -- -- -- 2 2
-166 Min. Max. -- 6 2.5 2.5 -- 1.5 1 -- -- 0 -- 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- 166 -- -- -- 3.5 -- -- 3.4 3.5 -- 3.4 -- -- -- -- -- -- -- -- -- -- -- -- 2 2
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc
tKQLZ tOEQ tOELZ tAS tWS tCES tSE
tKQHZ(2,3)
(2,3) (2,3)
tOEHZ
tADVS tDS tAH tHE tWH tCEH tADVH tDH tPDS tPUS Notes:
1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2.
12
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current Conditions ZZ VIH 2 2 2 0 Min. Max. 75 Unit mA cycle cycle cycle ns
SLEEP MODE TIMING
CLK
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All Inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z Don't Care
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
13
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
READ CYCLE TIMING
tKH tKL
CLK
tADVS tADVH
ADV
tKC
tAS tAH
Address A1 A2 A3
tWS tWH
WRITE
tSE tHE
CKE
tCES tCEH
CE
OE
tOEQ tOEHZ
Data Out
Q1-1
tOEHZ
tKQX
Q2-1
tKQ tKQHZ
Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4
NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care Undefined
14
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
WRITE CYCLE TIMING
tKH tKL
CLK
tKC
ADV
Address
A1
A2
A3
WRITE
tSE tHE
CKE
CE
OE
tDS
Data In
D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 D3-2
tDH
D3-3 D3-4
tOEHZ
Data Out
Q0-3 Q0-4
NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care Undefined
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
15
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
SINGLE READ/WRITE CYCLE TIMING
tKH tKL
CLK
tSE tHE tKC
CKE
Address
A1
A2
A3
A4
A5
A6
A7
A8
A9
WRITE
CE
ADV
OE
tOEQ tOELZ
Data Out
Q1
tDS tDH
Q3
Q4
Q6
Q7
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
D5
Don't Care Undefined
16
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
CKE OPERATION TIMING
tKH tKL
CLK
tSE tHE tKC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
CE
ADV
OE
tKQ tKQLZ tKQHZ
Data Out
Q1
tDS tDH
Q3
Q4
Data In
NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
D2
Don't Care Undefined
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
17
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
CE OPERATION TIMING
tKH tKL
CLK
tSE tHE tKC
CKE
Address
A1
A2
A3
A4
A5
WRITE
CE
ADV
OE
tOEQ tOELZ tKQHZ tKQ tKQLZ
Data Out
Q1
Q2
tDS tDH
Q4
Data In
D3
NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
D5
Don't Care Undefined
18
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
ORDERING INFORMATION (3.3V core/2.5V- 3.3V I/O) Commercial Range: 0C to +70C
Configuration 1Mx36 166 IS61NLP102436A-166TQ IS61NLP102436A-166TQL IS61NLP102436A-166B3 2Mx18 166 IS61NLP204818A-166TQ IS61NLP204818A-166TQL IS61NLP204818A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA Access Time Order Part Number Package
Industrial Range: -40C to +85C
Configuration 1Mx36 166 IS61NLP102436A-166TQI IS61NLP102436A-166TQLI IS61NLP102436A-166B3I IS61NLP204818A-166TQI IS61NLP204818A-166TQLI IS61NLP204818A-166B3I 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA Access Time Order Part Number Package
2Mx18 166
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
19
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0C to +70C
Configuration 1Mx36 166 IS61NVP102436A-166TQ IS61NVP102436A-166TQL IS61NVP102436A-166B3 IS61NVP204818A-166TQ IS61NVP204818A-166TQL IS61NVP204818A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA Access Time Order Part Number Package
2Mx18 166
Industrial Range: -40C to +85C
Configuration 1Mx36 166 IS61NVP102436A-166TQI IS61NVP102436A-166TQLI IS61NVP102436A-166B3I IS61NVP204818A-166TQI IS61NVP204818A-166B3I 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 165 PBGA Access Time Order Part Number Package
2Mx18 166
20
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. A 09/13/07
PACKAGING INFORMATION
Ball Grid Array Package Code: B (165-pin)
TOP VIEW
A1 CORNER 1
A B C D E F G H J K L M N P R
b (165X)
BOTTOM VIEW
A1 CORNER 9 8 7 6 5 4 3 2 1
A B C D
2
3
4
5
6
7
8
9
10
11
11 10
e
E F G
D D1
H J K L M N P R
e E1 E A2 A1 A
BGA - 13mm x 15mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.25 -- 14.90 13.90 12.90 9.90 -- 0.40
INCHES Min. Nom. Max.
165
Notes: 1. Controlling dimensions are in millimeters.
Min.
Nom. Max.
165 -- 0.33 0.79 15.00 14.00 13.00 10.00 1.20 0.40 -- 15.10 14.10 13.10 10.10 -- 0.50
-- 0.010 -- 0.587 0.547 0.508 0.390 -- 0.016
-- 0.031 0.591 0.551 0.512 0.394 0.039 0.018
0.047 -- 0.594 0.555 0.516 0.398 -- 0.020
0.013 0.016
1.00
0.45
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 06/11/03
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package) Package Code: TQ
D D1
E
E1
N
1
C e SEATING PLANE
L1 L
A2 A1 b
A
Symbol Ref. Std. No. Leads (N) 100 A -- 1.60 -- 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. o o C 0 7 0o 7o
Millimeters Min Max
Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 -- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o
Inches Min Max
-- 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o
Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PK13197LQ Rev. D 05/08/03

▲Up To Search▲

Price & Availability of IS61NVP102436A

	To Download IS61NVP102436A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .